Field of the Invention
The present invention relates to a method for planarizing a surface of an isolating layer that is deposited on a semiconductor body of an integrated semiconductor circuit configuration and whose surface lies on a higher level relative to the semiconductor body in first regions of the semiconductor circuit configuration than in second regions of the semiconductor circuit configuration.
In the fabrication of integrated circuits such as semiconductor memories, their surfaces must be planarized after certain processing steps before further processing steps are initiated. The planarizing usually occurs in a chemical mechanical polishing (CMP) step. An example of this is the masking of the active region (active area (AA) mask) with the subsequent isolation trench (IS) etching of this region in DRAM fabrication. After the AA masking the inactive regions are filled with silicon dioxide, what is known as a shallow trench isolation (STI) oxide, for electrical isolation and then planarized by a CMP step. It is known that the desired planarity cannot be achieved by a CMP step and specified CMP tools.
It is accordingly an object of the invention to provide a method for planarizing an isolating layer which overcomes the above-mentioned disadvantages of the prior art methods of this general type, with which it is possible to minimize levels between individual regions of the isolating layer and between the isolating layer and a top edge of silicon.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for planarizing a surface of an isolating layer deposited on a semiconductor body of an integrated semiconductor circuit configuration. The surface lies at a higher level in first zones of the integrated semiconductor circuit configuration than in second zones of the integrated semiconductor circuit configuration. The method includes the steps of covering the second zones with a block mask, and etching the isolating layer in the first zones.
The object is inventively achieved with a method of the above type by first covering the second zones with a block mask, and then subjecting the isolating layer to an etching process in the first zones.
In an advantageous development of the invention, the isolating layer is an STI layer formed of silicon dioxide. The level of the STI layer can be at least 10 nm higher in the first zones than in the second zones. The first zones can advantageously form a cell field, while a logic configuration is placed in the second zones.
Dry or wet chemical etching can be applied for the etching process with which the isolating layer in the first zones is etched back. The etching process can be performed before or after the removal of a silicon nitride layer that covers the semiconductor body outside the isolating layer.
A suitable material can be employed for the block mask, such as a resist, a varnish, etc.
What is essential to the inventive method is that zones with a lower level, such as a logic area or a thin oxide zone, are first covered with a block mask. The regions with a higher level, such as an active region like a cell field or a thick oxide zone, are then etched back by a dry or wet chemical process. The etching can be performed before or after the removal of a nitride layer or some other isolating layer that may still be present in the active zone or cell field, i.e. before or after a nitride strip. A CHF3/CF4 oxide etching chemistry is preferably utilized for the etching for which a reactive ion etching (RIE) can be utilized.
With the inventive method, the planarization can be appreciably improved after a CMP step by dry and wet chemical etching with the aid of the block mask. The level in the individual zones can be reduced by the selective etching with the aid of the block mask, so that the planarity comes optimally close to the desired planarity for regions with low coverage densities, such as in the logic area, and for regions with high coverage density, such as in the cell field. If necessary, it is possible to remove the block mask from the second zones after an etching process in the first zones and to perform an additional dry or wet chemical etching procedure in the second zones, potentially together with the first zones.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method for planarizing an isolating layer, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.